Bucket brigade devices have been used for analog signal processing applications in which the signal propagates from the input node to the output node via a chain of shift registers composed of bucket brigade devices. The bucket brigade device is an analog shift register comprising a chain of storage capacitors and charge transfer circuits. As disclosed by Sangster in U.S. Pat. No. 3,745,383, the bucket brigade analog shift register of the prior art employing MOSFET devices, as shown in FIG. 1, uses two complementary clocks with a frequency equal to the sampling frequency applied to the controlling gates alternately. The signal delay can thus be accurately controlled, or if required, can be changed electronically. Because there are no DC gate currents, signal attenuation is negligible even after hundreds of stages, and no amplifiers are necessary.
In the prior art circuit shown in FIG. 1, the input signal source E.sub.in is connected to the bucket brigade circuit at the source of FET device 4. The gate of FET device 4 is controlled by the V1 clock pulse as shown in FIG. 2. The input signal E.sub.in from the input signal source 2 is transferred during V1 clock time as a unit of charge through the FET device 4 to the node 18 connecting the drain of device 4 to the source of FET device 6. FET device 6 has its gate connected to the second clock waveform V2 as shown in FIG. 2. The charge stored at node 18 as transferred to node 20 during V2 time via device 6. The unit of charge representing the input signal E.sub.in is propagated down the chain of FET devices 4, 6, 8, and 10 by the alternate operation of their respective gates by means of the clock pulses V1 and V2. The unit of charge representing the input signal ultimately is output at the output node 24. It is then necessary for the charge to be transferred from the input node to the output node with as little loss as possible. The voltage source 14 provides the bias for the circuit. FET type bucket brigade devices can be fabricated using standard MOSFET processing techniques.
Transfer efficiency and dynamic range are paramount criteria in the design of a bucket brigade device. As is shown in the prior art circuit of FIG. 1, associated with each FET device are four characteristic capacitances; the gate to source capacitance C.sub.GS, the source to substrate capacitance C.sub.SS, the drain to substrate capacitance C.sub.DS, and the gate to drain capacitance C.sub.GD. Due to the capacitances at node 18 in the prior art bucket brigade device of FIG. 1, charge representing the input signal at node 18, cannot be maintained at an optimum level because of voltage pull-back and a charge redistribution during the fall time of the V1 clock pulse. Consequently, the voltage at the end of the phase time at any subsequent node is lower compared to that at the input node 16. This problem of voltage pull-back and charge redistribution at node 18 can be explained as follows.
For efficient charge transfer from the source to drain of an FET device, the gate voltage must be one threshold voltage V.sub.t (including the substrate body effect) higher than the voltage applied to the source. This is illustrated in FIG. 1 and FIG. 2 such that EQU V1 &gt; E.sub.in + V.sub.t. (1)
where V.sub.1 = 8.5V, and E.sub.in = 5.0V. This illustration is for N-channel LSI FET circuits.
During the phase V1 time, the input signal E.sub.in is fully transferred to the node 18 via FET device 4. The nodal voltage is represented by the charge stored in the nodal capacitance consisting of C.sub.DS and C.sub.GD of FET 4 and C.sub.GS and C.sub.SS of FET 6. C.sub.GD also acts as a coupling capacitor between clock V1 and the node 18. Thus, the nodal charge will be influenced by the fluctuation of V1. When the clock V1 is pulling back, the nodal charge remains practically unchanged until V1 falls below E.sub.in. Then the FET device 4 stops conducting and the nodal charge at the node 18 flows out and follows the pull-back of V1 through the coupling capacitance C.sub.GD. The resultant nodal voltage at the end of V1 phase time will be lowered due to the charge redistribution among all capacitors. The magnitude of voltage loss due to charge redistribution can be calculated as ##EQU1## Thus the resultant nodal voltage at the end of V1 phase time becomes ##EQU2## It is evident that the resultant voltage at the node 18 is always less than E.sub.in since C.sub.GD is always present in the FET devices. This known circuit suffers from the disadvantages that the optimum charge transfer cannot be achieved and the dynamic range is reduced as a result of charge redistribution due to clock pull-back.
Thus it is seen that what the prior art requires is a bucket brigade device which has a higher transfer efficiency and dynamic range.